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document number: mma3201keg rev 2, 11/2012 freescale semiconductor data sheet: technical data ? 2009, 2011, 2012 freescale semiconductor, inc. all rights reserved. surface mount micromachined accelerometer the mma3201 series of dual axis (x and y) silicon capacitive, micromachined accelerometers features signal conditioning, a 4-pole low pass filter and temperature compensatio n, and separate outputs for the two axes. zero-g offset full scale span and filter cut-off are factor y set and require no external devices. a full system self-test capability verifies system functionality. features ? sensitivity in two separate axes: 40g x-axis and 40g y-axis ? integral signal conditioning ? linear output ? ratiometric performance ? 4th order bessel filter preserves pulse shape integrity ? calibrated self-test ? low voltage detect, clock monitor, and eprom parity check status ? transducer hermetically sealed at wafer level for superior reliability ? robust design, high shocks survivability ? qualified aec-q100, rev. f grade 2 (-40 ? c/ +105 ?c) typical applications ? vibration monitoring and recording ? impact monitoring ? appliance control ? mechanical bearing monitoring ? computer hard drive protection ? computer mouse and joysticks ? virtual reality input devices ? sports diagnostic devices and systems ordering information device name temperature range case no, package mma3201eg ?40 to +125c 475a-02 soic-20 mma3201egr2 ?40 to +125c 475a-02 soic-20, tape & reel mma3201keg* ?40 to +125c 475a-02 soic-20 mma3201kegr2* ?40 to +125c 475a-02 soic-20, tape & reel *part number sourced from a different facility. mma3201keg mma3201keg: xy-axis sensitivity micromachined accelerometer 40 g keg suffix (pb-free) 20-lead soic case 475a-02 g-cell sensor integrator gain filter temp comp s elf-test control logic & eprom trim circuits clock generator oscillator v dd v out v ss st status figure 1. simplified accelero meter functional block diagram figure 2. pin connections n/c n/c n/c n/c st x out status v ss v dd av dd 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 gnd n/c n/c n/c n/c n/c n/c n/c n/c y out
sensors 2 freescale semiconductor, inc. mma3201keg electro static discharge (esd) warning: this device is sensi tive to electrostatic discharge. although the freescale accelerometers contain internal 2 kv esd protection circuitry, extra precaution must be taken by the user to protect the ch ip from esd. a charge of over 2000 volts can accumulate on the human body or associated test equipment. a charge of this magnitude can alter the performance or cause failure of the chip. when handling the accelerometer, proper esd precautions should be followed to avoid exposing the device to discharges which may be detrimental to its performance. table 1. maximum ratings (maximum ratings are the limits to which the devic e can be exposed without c ausing permanent damage.) rating symbol value unit powered acceleration (all axes) g pd 1500 g unpowered acceleration (all axes) g upd 2000 g supply voltage v dd ?0.3 to +7.0 v drop test (1) 1. dropped onto concrete surface from any axis. d drop 1.2 m storage temperature range t stg ?40 to +125 c
sensors freescale semiconductor, inc. 3 mma3201keg table 2. operating characteristics (unless otherwise noted: ?40c ?? t a ?? +105c, 4.75 ?? v dd ?? 5.25, x and y channels, acceleration = 0g, loaded output. (1) ) characteristic symbol min typ max unit operating range (2) supply voltage (3) supply current operating temperature range acceleration range v dd i dd t a g fs 4.75 6 ?40 ? 5.00 8 ? 45 5.25 10 +125 ? v ma c g output signal zero g (t a = 25c, v dd = 5.0 v) (4) zero g sensitivity (t a = 25c, v dd = 5.0 v) (5) sensitivity bandwidth response nonlinearity v off v off,v s s v f ?3db nl out 2.35 0.46 v dd 47.5 9.3 360 ?1.0 2.5 0.50 v dd 50 10 400 ? 2.65 0.54 v dd 52.5 10.7 440 +1.0 v v mv/g mv/g/v hz % fso noise rms (.01 hz ? 1 khz) power spectral density clock noise (without rc load on output) (6) n rms n psd n clk ? ? ? ? 110 2.0 2.8 ? ? mvrms ? v/(hz 1/2 ) mvpk self-test output response (7) input low input high input loading (8) response time (9) g st v il v ih i in t st 10 v ss 0.7 ?? v dd ?30 ? 12 ? ? ?110 2.0 14.4 0.3 ?? v dd v dd ?300 ? g v v ? a ms status (10), (11) output low (i load = 100 ? a) output high (i load = 100 ? a) v ol v oh ? v dd ? 0.8 ? ? 0.4 ? v v minimum supply voltage (lvd trip) v lvd 2.7 3.25 4.0 v clock monitor fail detection frequency f min 50 ? 260 khz output stage performance electrical satura tion recovery time (12) full scale output range (i out = 200 ? a) capacitive load drive (13) output impedance t delay v fso c l z o ? 0.25 ? ? 0.2 ? ? 300 ? v dd ?0.25 100 ? ms v pf ? mechanical characteristics transverse sensitivity (14) package resonance v xz,yz f pkg ? ? ? 10 5.0 ? % fso khz 1. for a loaded output the measurements are observed after an rc filter consisting of a 1 k ? resistor and a 0.01 ? f capacitor to ground. 2. these limits define the range of operation fo r which the part will meet specification. 3. within the supply range of 4.75 and 5.25 volts, the device operat es as a fully calibrated linear accelerometer. beyond these supply limits the device may operate as a linear device but is not guaranteed to be in calibration. 4. the device can measure both + and ? acceleration. with no input acceleration the output is at mi dsupply. for positive acceler ation the output will increase above v dd /2 and for negative acceleration th e output will decrease below v dd /2. 5. the device is calibrated at 20g. 6. at clock frequency ? 70 khz. 7. ? v off calculated with typical sensitivity. 8. the digital input pin has an internal pull-down current source to prevent inadvertent self test initiation due to external bo ard level leakages. 9. time for the output to reach 90% of its final value after a self-test is initiated. 10. the status pin output is not valid following power-up until at least one rising edge has been a pplied to the self-test pin. the status pin is high whenever the self-test input is high, as a means to check the connectivity of the se lf-test and status pins in the application. 11. the status pin output latches high if a low voltage detection or clock frequency failure occurs, or the eprom parity changes to odd. the status pin can be reset low if the self-test pi n is pulsed with a high input for at least 100 ? s, unless a fault conditi on continues to exist. 12. time for amplifiers to recover after an ac celeration signal causing them to saturate. 13. preserves phase margin (60) to guarantee output amplifier stability. 14. a measure of the device's ability to reject an acce leration applied 90 from the true axis of sensitivity.
sensors 4 freescale semiconductor, inc. mma3201keg principle of operation the freescale accelerometer is a surface-micromachined integrated-circuit accelerometer. the device consists of a surface micromachined capacitive sensing cell (g-cell) and a cmos signal conditioning asic contained in a single integrated circuit package. the sensing element is sealed hermetically at the wafer level using a bulk micromachined ?cap'' wafer. the g-cell is a mechanical structure formed from semiconductor materials (polysilicon) using semiconductor processes (masking and etching). it can be modeled as two stationary plates with a mo veable plate in-between. the center plate can be deflected from its rest position by subjecting the system to an acceleration ( figure 3 ). when the center plate deflects, the distance from it to one fixed plate will increase by the same amount that the distance to the other plate decreases. the change in distance is a measure of acceleration. the g-cell plates form two back-to-back capacitors ( figure 4 ). as the center plate moves with acceleration, the distance between the plates changes and each capacitor's value will change, (c = a ? /d). where a is the area of the plate, ? is the dielectric constant, and d is the distance between the plates. the cmos asic uses switched capacitor techniques to measure the g-cell capacitors and extract the acceleration data from the difference between the two capacitors. the asic also signal conditions and filters (switched capacitor) the signal, providing a high le vel output voltage that is ratiometric and proportional to acceleration. special features filtering the freescale accelerometers contain an onboard 2-pole switched capacitor filter. a be ssel implementation is used because it provides a maximally flat delay response (linear phase) thus preserving pulse shape integrity. because the filter is realized using switched capacitor techniques, there is no requirement for external passive components (resistors and capacitors) to set the cut-off frequency. self-test the sensor provides a self-t est feature that allows the verification of the mechanical and electrical integrity of the accelerometer at any time before or after installation. this feature is critical in applications such as automotive airbag systems where system integrity must be ensured over the life of the vehicle. a fourth ?plate'' is used in the g-cell as a self- test plate. when the user applies a logic high input to the self- test pin, a calibrated potential is applied across the self-test plate and the moveable plate. the resulting electrostatic force causes the cent er plate to deflect. the resultant deflection is measured by the accelerometer's control asic and a proportional output voltage results. this procedure assures that both the mechanical (g-cell) and electronic sections of the accelerometer are functioning. status freescale accelerometers include fault detection circuitry and a fault latch. the status pi n is an output from the fault latch, or'd with self-test, and is set high whenever the following event occurs: ? parity of the eprom bits becomes odd in number. the fault latch can be reset by a rising edge on the self-test input pin, unless one (or more) of the fault conditions continues to exist. acceleration figure 3. transducer physical model figure 4. equivalent circuit model f e 1 2 -- - ? a v 2 d 2 ------ = ?? ?? ??
sensors freescale semiconductor, inc. 5 mma3201keg basic connections pinout description figure 5. soic accelerometer with recommended connection diagram pcb layout figure 6. recommended pcb layout for interfacing accelerometer to microcontroller notes: 1. use a 0.1 ? f capacitor on v dd to decouple the power source. 2. physical coupling distance of the accelerometer to the microcontroller should be minimal. 3. place a ground plane beneath the accelerometer to reduce noise, the ground plane should be attached to all of the open ended terminals shown in figure 6 . 4. use an rc filter of 1 k ? and 0.01 ? f on the output of the accelerometer to minimize clock noise (from the switched capacitor filter circuit). 5. pcb layout of power and ground should not couple power supply noise. 6. accelerometer and microcontroller should not be a high current path. 7. a/d sampling rate and any external power supply switching frequency should be se lected such that they do not interfere with the internal accelerometer sampling frequency. this will prevent aliasing errors. pin no. pin name description 1 thru 3 ? leave unconnected. 4 ? no internal connection. leave unconnected. 5 st logic input pin used to initiate self-test. 6x out output voltage of the accelerometer. x direction. 7 status logic output pin to indicate fault. 8v ss the power supply ground. 9v dd the power supply input. 10 av dd power supply input (analog). 11 y out output voltage of the accelerometer. y direction. 12 thru 16 ? used for factory trim. leave unconnected. 17 thru 19 ? no internal connection. leave unconnected. 20 gnd ground. n/c n/c n/c n/c st x out status v ss v dd av dd 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 gnd n/c n/c n/c n/c n/c n/c n/c n/c y out v dd logic input c1 0.1 ? f 5 9 10 8 st v dd av dd v ss y out mma3201keg 7 6 11 status x output signal r1 1 k ? c2 0.01 ? f r2 1 k ? c3 0.01 ? f y output signal x out status st x out y out v ss v dd accelerometer p1 p0 a/d in a/d in v rh v ss v dd microcontroller c 0.1 ? f c0.1 ? f power supply c 0.1 ? f 0.1 ? f 0.1 ? f r 1 k ? r c c 1 k ?
sensors 6 freescale semiconductor, inc. mma3201keg n/c n/c n/c n/c st x out status v ss v dd av dd 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 gnd n/c n/c n/c n/c n/c n/c n/c n/c y out +y ?x +x direction of earth?s gravity field.* * when positioned as shown, the earth?s gravity wi ll result in a positive 1g output in the x channel. front view side view top view static acceleration sensing direction dynamic acceleration sensing direction acceleration of the package in the +x and +y direction (center plates move in the -x and -y direction) will result in an increase in the x and y outputs. 20-pin soic package n/c pins are recommended to be left floating 11 12 13 14 1516 17 18 19 20 10 9 8 7 6 5 4 3 2 1 activation of self test moves the center plates in the -x and -y direction, resulting in an increase in the x and y outputs. ?y
sensors freescale semiconductor, inc. 7 mma3201keg minimum recommended footprint fo r surface mounted applications surface mount board layout is a critical portion of the total design. the footprint for the surface mount packages must be the correct size to ensure proper solder connection interface between the board and the package. with the correct footprint, the packages will self-align when subjected to a solder reflow process. it is always recommended to design boards with a solder mask layer to avoid bridging and shorting between solder pads. figure 7. footprint soic-20 (case 475a-01) 0.380 in. 9.65 mm 0.050 in. 1.27 mm 0.024 in. 0.610 mm 0.080 in. 2.03 mm
notes: 1. 2. 3. 4. 5. 6. 7. all dimensions are in millimeters. interpret dimensions and tolerances per asme y14.5m, 1994. this dimension applies to metallized terminal and is measured between 0.25mm and 0.30mm from terminal tip. this dimension represents terminal full back from package edge up to 0.1mm is acceptable. coplanarity applies to the exposed heat slug as well as the terminal. radius on terminal is optional. minimum metal gap 0.2mm. (45?) 16x 0.1 4 detail m pin 1 index area 6 b c 0.10 2x 2x c 0.10 a 6 m m (0.203) c 0.1 c 0.08 c seating plane 5 detail g view rotated 90? clockwise (1) (0.5) (0.102) 1.45?.1 exposed die attach pad 13 4 1 16 12x 9 12 85 m 0.1 c m 0.05 c a b 16x 0.63 0.43 c 0.1 a b view m-m detail m pin 1 index detail g c 0.1 a b 16x 0.60 0.40 1 4.24 4.04 4.24 4.04 0.5 3 sensors 8 freescale semiconductor, inc. mma3201keg package dimensions 98asa10651d issue o
sensors freescale semiconductor, inc. 9 mma3201keg 98asa10651d issue o 16-lead qfn date 06/28/04 case 1622-01 issue o notes: 1. 2. 3. 4. 5. 6. 7. all dimensions are in millimeters. interpret dimensions and tolerances per asme y14.5m, 1994. this dimension applies to metallized terminal and is measured between 0.25mm and 0.30mm from terminal tip. this dimension represents terminal full back from package edge up to 0.1mm is acceptable. coplanarity applies to the exposed heat slug as well as the terminal. radius on terminal is optional. minimum metal gap 0.2mm. (45?) 16x 0.1 4 detail m pin 1 index area 6 b c 0.10 2x 2x c 0.10 a 6 m m (0.203) c 0.1 c 0.08 c seating plane 5 detail g view rotated 90? clockwise (1) (0.5) (0.102) 1.45?.1 exposed die attach pad 13 4 1 16 12x 9 12 85 m 0.1 c m 0.05 c a b 16x 0.63 0.43 c 0.1 a b view m-m detail m pin 1 index detail g c 0.1 a b 16x 0.60 0.40 1 4.24 4.04 4.24 4.04 0.5 3
sensors 10 freescale semiconductor, inc. mma3201keg table 4. revision history revision number revision date description of changes 2 11/2012 ? table 2. operating characteristics, add ed footnote for self-test ou tput response, updated page 4: principle of operation
mma3201keg rev 2 11/2012 information in this document is provided solely to enable system and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fabr icate any integrated circuits based on the information in this document. freescale reserves the right to make changes without further notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including ?typicals,? must be validated for each customer application by customer?s technical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/salestermsandconditions. freescale, the freescale logo, energy efficient solutions logo, are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. xtrinsic is a trademark of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? 2012 freescale semiconductor, inc. how to reach us: home page: freescale.com web support: freescale.com/support

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